The widespread adoption of FPGA-accelerated com-
puting in embedded and cloud environments introduces new
side-channel threats due to shared hardware resources. This
work investigates DRAM access patterns as a leakage source to
fingerprint CPU activity, examining both SoC-FPGA and cloud-
based co-processor models. In SoC environments, cache-miss-
induced DRAM activity generates measurable power fluctuations
that can be remotely observed. While previous research has
detected these fluctuations using external electromagnetic probes
for side-channel-based disassembly, we assess whether embedded
FPGA sensors can achieve similar results, enabling attackers
to infer CPU operations without physical access. However, in
cloud-based co-processor models, where FPGA-CPU interactions
occur over PCIe and RDMA, large-scale power management
appears to significantly lower the Signal-to-Noise Ratio (SNR),
potentially making power side channels more challenging to
exploit compared to SoC-FPGAs. Given this uncertainty, we
investigate the feasibility of power-based leakage while also
exploring timing-based side channels leveraging PCIe contention
and RDMA latency variations, which have been shown to reveal
workload characteristics. By evaluating both power and timing
leakage across these architectures, we comprehensively assess
side-channel risks in FPGA-accelerated platforms and emphasize
the need for stronger isolation mechanisms.